OptiMem - Advanced Virtual Memory Simulator

Introduction to Virtual Memory

Virtual memory is a memory management technique that provides an "idealized abstraction" of the storage resources that are actually available on a given machine.

Key Benefits:

Allows execution of processes larger than physical memory
Simplifies programming by abstracting memory hierarchy
Provides memory protection between processes
Enables more efficient use of physical memory

Physical Memory

Actual RAM chips in the computer with fixed size.

Virtual Memory

Illusion of a very large memory space provided by the OS.

In the simulator, you'll see how virtual addresses are translated to physical addresses through page tables and how page replacement algorithms manage memory.

Paging Concepts

Key Definitions:

Page: Fixed-size block of virtual memory
Frame: Fixed-size block of physical memory
Page Table: Data structure mapping virtual to physical addresses

Address Translation

Virtual addresses are split into:

Page number (index into page table)
Page offset (position within page)

Virtual Address = [Page Number | Offset]

Page Table Entry

Each entry contains:

Frame number
Present/absent bit
Protection bits
Modified (dirty) bit
Referenced bit

Try It Out:

In the simulator, configure:

Memory Size = 64KB
Page Size = 4KB
Access Sequence = 1,2,3,4,1,2,5,1,2,3,4,5

Observe how the page table maps virtual pages to physical frames.

Page Replacement Algorithms

Algorithm Comparison:

Algorithm	Complexity	Page Fault Rate	Real-world Use
FIFO	Low	High	Simple systems
LRU	Medium	Medium	General purpose
OPT	High	Low (ideal)	Benchmarking only
Clock	Medium	Medium-Low	Modern OS

FIFO (First-In-First-Out)

Replaces the page that has been in memory the longest.

Pros: Simple to implement
Cons: Suffers from Belady's anomaly

LRU (Least Recently Used)

Replaces the page that hasn't been used for the longest time.

Pros: Good performance
Cons: Hard to implement efficiently

Hands-on Activity:

Run the simulator with the same access sequence but different algorithms
Compare the page fault counts for each algorithm
Notice how OPT gives the fewest faults (but isn't practical)
Observe how LRU approximates OPT's performance

Translation Lookaside Buffer (TLB)

TLB Basics:

Special cache for page table entries
Stores recent virtual-to-physical address translations
Typical size: 64-1024 entries
Access time: 1-10 cycles (vs 100+ for main memory)

Address Translation Flow

CPU generates virtual address
Check TLB (hit → physical address available)
TLB miss → consult page table in memory
Update TLB with new translation
Access physical memory

TLB Entry Structure

[Tag | Frame Number | Valid Bit | Protection Bits | ...]

TLBs are typically fully associative or set-associative to maximize hit rate.

Simulator Demonstration:

In the simulator:

Set Memory Size = 128KB, Page Size = 8KB
Use access sequence: 1,2,3,4,1,2,5,6,1,2,3,4,5,6
Run with LRU algorithm
Watch how TLB hits increase after initial misses

Memory Fragmentation

Internal Fragmentation

Wasted space within allocated memory blocks.

Cause: Fixed-size pages mean processes may not need the entire page.

Example: 5KB process in 8KB page → 3KB wasted

External Fragmentation

Wasted space between allocated blocks.

Cause: Variable-size allocations leave unusable gaps.

Example: Three 4KB frames free, but can't allocate 8KB contiguous block

How Paging Helps:

Eliminates external fragmentation (all frames are same size)
Internal fragmentation limited to last page of process
Average internal fragmentation = 0.5 * page size

Simulation Exercise:

Set Memory Size = 64KB, Page Size = 4KB
Use access sequence: 1,2,3,4,5,6,7,8,1,2,3,4
Run with FIFO algorithm
Observe the fragmentation metrics in the results
Try different page sizes to see effect on fragmentation

Running Simulations

Step-by-Step Guide:

Configure Parameters:
- Memory Size (total physical memory)
- Page Size (size of each page/frame)
- Algorithm (FIFO, LRU, OPT, etc.)
Set Access Sequence:
- Comma-separated list of page numbers
- Example: "1,2,3,4,1,2,5,1,2,3,4,5"
Run Simulation:
- Start: Runs continuously
- Pause: Halts simulation
- Step: Advances one step at a time
- Reset: Returns to initial state
Analyze Results:
- Page fault count
- TLB hit/miss ratio
- Memory map visualization
- Performance charts

Sample Experiments

Belady's Anomaly:
Show FIFO producing more faults with more frames

Sequence: 1,2,3,4,1,2,5,1,2,3,4,5
LRU vs FIFO:
Compare on same sequence

Sequence: 1,2,3,4,2,1,5,6,2,1,2,3,7,6

Advanced Features

Speed Control: Adjust simulation speed
Export: Save results as JSON
Fullscreen: Expand visualization
Heatmap: View frequently replaced pages

Learning Objectives:

Understand relationship between page size and fragmentation
Compare algorithm performance on different access patterns
Visualize how TLB improves performance
Recognize symptoms of memory thrashing

Real-world Memory Systems

Modern OS Implementations

Linux: Uses modified Clock algorithm ("Second Chance")
Windows: Uses Working Set-based algorithm
macOS: Uses LRU approximation with activity counters

Multi-level Page Tables

Modern systems use hierarchical page tables to save space:

Page directory points to page tables
Only allocate page tables for used memory regions
Common in x86 (2-level) and ARM (3-level)

Inverted Page Tables

Used in some architectures to save space:

One entry per physical frame (not per virtual page)
Uses hash table for lookup
Used in PowerPC and some ARM systems

Challenge: Slower lookups but saves memory

Performance Considerations

TLB Coverage: (TLB size × page size) determines how much memory can be accessed without TLB misses
Page Size Tradeoffs:
- Larger pages → fewer TLB misses but more internal fragmentation
- Smaller pages → less fragmentation but more TLB misses
Superpages: Some systems support larger pages (2MB, 1GB) for frequently accessed regions

Beyond the Simulator

Real systems add complexity like:

Memory-mapped files
Copy-on-write pages
Swapping to disk
NUMA (Non-Uniform Memory Access) considerations
Memory compression (in macOS and Linux)

Master Virtual Memory with Interactive Simulations

Key Features

Multiple Algorithms

Comprehensive Metrics

Educational Focus

Memory Simulator

Simulation Configuration

Visualization Preview

Simulation Results

Page Faults Over Time

Hit/Miss Ratio

Memory Map

Page Table

TLB (Translation Lookaside Buffer)

Virtual Memory Tutorial

Topics